The present invention generally relates to methods for manufacturing field effect transistors (FETs). More specifically, the invention relates to the manufacture of FETs having extremely short gate lengths.
In field effect transistors, particularly MESFETs or HEMTS, the spacing between the gate and the contact layer should be kept short at the source side so that the parasitic source resistance is kept low. On the other hand, the spacing between the gate and the contact layer should be relatively large at the drain side, so that the breakdown voltage between the gate and the drain is adequately high and the gate-drain capacitance is optimally low at the same time.
Up to now, self-aligning manufacturing methods were utilized for addressing these issues when the required breakdown voltage was not excessively high. The spacing between the gate and the n.sup.+ contact layer thereby remained the same at the source and drain sides (i.e., symmetrical position of source and drain around the gate).
For higher breakdown voltages, the spacing to the contact layer was enlarged at the drain side with an additional phototechnique adjustment step. For example, U.S. Pat. Nos. 4,196,439 and 4,956,308, incorporated herein by reference, disclose such methods. It is proposed in U.S. Pat. No. 4,300,148, also incorporated herein by reference, to make the thickness of the active layer at the dram side of the gate so thin or, respectively, to make it so lightly doped that it can just accept (or absorb) the maximum of the possible current under the gate.